The invention relates to two port random access memories, RAMs, wherein data stored by row and column addresses are read from or written into the RAM serially through one of the two ports by physical column sequential transferring.
Random access memories having a second input/output (I/O) port have been used in mapped raster display apparatus to provide data from a random access memory, such as a dynamic random access memory, DRAM, to form a CRT image on a display which has a finite decay time before the image will fade. In such an application, a continuous data stream must be read from the memory in order to keep the display refreshed.
It is also conventional to write data through the second input/output port to the DRAM. As will be explained in greater detail hereinafter, such a random access memory is usually provided with at least one internal row buffer register which can transfer an entire row of data from the second input/output port to the RAM or transfer an entire row of data from the RAM to the second input/output port.
The DRAM stores an electrostatic charge on a capacitor at the intersection of each row and column to represent a binary number bit which is to be stored. WRITE and READ circuits are provided to access each capacitor element and apply the proper charge to the capacitor element for representing a binary 1 or 0. The capacitor elements are addressed by a plurality of row address bits and a plurality of column address bits supplied to the memory. The DRAM requires a refresh operation to maintain the proper electrostatic charge on the capacitor. The clock and address structure for the DRAM provides for periodic refresh of the column, typically every two to four milliseconds in response to an externally applied signal. The external signals applied to a DRAM include the row address signal, RAS, and the column address signal, CAS. The random access memory provides in response to these externally applied signals, a recharge function and timing signals for addressing each memory cell in response to an additionally supplied address signal. A first input/output port, I/O, receives and delivers data in response to a WRITE and READ command, respectively, also applied externally to the DRAM.
When the DRAM is used as a display random access memory in a mapped raster display apparatus, the display refresh function for refreshing the CRT image interferes with the updating of the memory data by usurping the input/output port at which time no new data may be stored. Therefore, updating a real time display using a mapped raster technique becomes difficult because of the limitation imposed from time sharing of the memory between updating information to be written into the memory and reading out data for refresh of the display.
The limitations imposed on memory usage by virtue of all traffic passing to the memory through a single input/output port have been eliminated with the advent of the two port random access memory. Such a memory is described in U.S. Pat. No. 4,541,075 which issued on Sept. 10, 1985 to Dill et al and which is assigned to the assignee of the instant application.
FIG. 1 represents a conventional two port random access memory such as described in the aforementioned Dill et al patent. The random access memory is provided with an internal row buffer register 25 which can transfer a row of data to and from the DRAM cells forming the matrix 11. The row buffer registers are connected to extensions of the column bit lines from the bi-directional sense amplifiers 17 of the RAM to transfer rows of data in parallel. A second input/output port 24 is provided on the RAM chip to serially receive the row buffer register contents or data to be written through buffer register 25 to the DRAM cells upon receipt of appropriate external pulse signals when a serial mode is selected. When a row is addressed and a READ operation is desired, a READ transfer pulse is applied to terminal 26 from a source external to the RAM, to transfer the row word to the row buffer register 25. A subsequent signal applied to the row buffer shift register will clock the contents of the register to a second input/output port 24 in the sequence determined by the physical column sequence.
The memory as depicted in FIG. 1 may advantageously be used in a bit mapped display device as the result of the block transfer of data into the row buffer register 25. The second input/output port 24 is then used to supply the refresh information necessary to maintain the CRT display refreshed. The primary output port 23 may therefore be used to update the memory with the new pixel data for later display without incurring delays from tying up the primary input/output port with refresh information for the display. In addition, the updating of the display memory contents in the main memory while refreshing the display from the row buffer will not result in interference problems for the image.
The two port random access memory may, of course, also be used to drive other types of output devices such as printers, disks and communications peripheral equipment. Additionally, as discussed in the aforementioned Dill et al patent, the two port random access memory may permit not only the reading out of data through the second input/output port but may also permit the writing of data through the second port to the memory cells.
As illustrated in FIG. 1, conventional two port RAMS wire extensions of the bit lines of the matrix array 11 to stages of the row buffer 25. That is, each bit line is physically extended and routed to a single shift register stage of the row buffer. This creates a fixed relationship between the primary port addressing and the secondary port shift position. The arrangement precludes the use of column redundant RAMS in a two port RAM wherein data is read or written serially through the secondary input/output port by physical column sequential accessing.
Column redundancy is a conventional technique for producing fault tolerant RAMS thus increasing RAM chip yields. During manufacturing, defective bit lines and associated memory cells are made unselectable by altering the RAM chip's internal addressing. Various techniques are known for altering the chip's internal addressing. Address modification may, for example, be accomplished with a polysilicone fuse scheme. The modified addressing points to a spare or redundant column and its associated bit line whenever the original defective bit line is externally addressed. Invoking column redundancy alters the serial data at the secondary output port in response to physical column sequential accessing. The present invention overcomes this limitation on the use of a column redundant random access memory in a two port RAM.